This invention relates to an error detection apparatus and more particularly to an error detection apparatus suitable for detecting block errors. A block error is an error in at least three of the bits in a set of bits. The invention is particularly applicable to detecting and correcting single bit errors, detecting double bit errors in a data word, detecting single block errors in a data word, and detecting a three or more bit burst error in a block or in a (b-1) bit block where b is the number of bits in a data block. The (b-1) bit block is contained in a data block or may extend across the boundary of two data blocks in the data word.
The following systems (1) and (2) are known conventionally as an error correction/detection system using SEC-DED-SbED codes (Single bit Error Correcting-Double Bit Error Detecting--Single b bit byte Error Detecting Codes):
(1) A system using the codes described on pages 593-598 of the journal of Electrocommunication Society, May, 1984, Japan.
(2) A system using the codes described on page 129 of IBM J.R&D, Vol. 28, No. 2, March, 1984.
The SEC-DED-SbED code is the code obtained by adding the detection capacity of the mass of a plurality (b) of bits such as a byte to a 1-bit error correction/2-bit error detection code (SEC-DED code) that is widely used for a main memory unit. This code is helpful in improving the reliability of a semiconductor memory devices using a memory element having data output of a plurality of bits. In the new SEC-DED-SbED codes described in the item (a), the maximum code bit length L.sub.0 is given by EQU L.sub.0 =(b+2).multidot.b.multidot.2.sup.r-b-2
where r is the number of inspection bits (r.gtoreq.b+2) and b is a byte length.
When the byte length b.ltoreq.16 bits, it has a code length longer than the conventional codes. When the number of inspection bits r=b+2, it provides a circulating minimum weight code suitable for improving the operation and packaging density of LSI for the coding/decoding circuit. In the meantime, it may be required to detect block errors for block division of two or more kinds of blocks. When, for example, an IC memory of a 4-bit structure is driven by a driver IC of a 3-bit structure, it is desired to detect the block error for the 4-bit block and at the same time, to detect also the block error for the 3-bit block. In this case, if the SEC-DED-SbED code is constituted according to the prior art technique described above, the 4-bit block error can be detected but the 3-bit block error spreading over the 4-bit blocks cannot be detected generally.